The present invention relates generally to semiconductor fabrication and more specifically to fabrication of electrostatic discharge device (ESDs).
The current practice to optimize input/output (I/O) device electrostatic discharge device (ESD) capability is to use an additional ESD implant. Thus an additional masking step is required which increases cost.
U.S. Pat. No. 5,953,190 to Rees et al. describes an electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit including a logic circuit.
U.S. Pat. No. 5,837,571 to Pathak describes a method to resolve the problem of low drain/source breakdown voltage (BVdss) in small geometry devices with thin gate oxide. One method improves the drain diffusion profile implanting through disjoint NSD/NWELL windows in the extended drain region. Other methods include building a number of side wall oxide layers, impurity compensation or oxygen implantation.
U.S. Pat. No. 5,618,740 to Huang describes a method of fabricating CMOS output buffer with enhanced ESD resistance. Core transistors are provided with punch-through pockets while the input/output transistors are not provided with punch-through pockets. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.
U.S. Pat. No. 5,529,941 to Huang describes a method of fabricating an integrated circuit by fabricating: at least one functional MOSFET with a hot electron resistant structure including a lightly doped drain; fabricating at least one output MOSFET with an ESD resistant structure including a gate means without associated spacers; and electrically coupling at least one functional MOSFET to at least one output MOSFET.
U.S. Pat. No. 5,728,612 to Wei et al. describes a process for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps.
U.S. Pat. No. 5,496,751 to Wei et al. describes a method of fabricating an ESD and hot carrier resistant integrated circuit structure.
U.S. Pat. No. 5,631,485 to Wei et al. describes a an ESD and hot carrier resistant integrated circuit structure.
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of fabricating electrostatic discharge devices.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region. An HV-LDD implant is performed into the structure adjacent the second device gate and the HV-I/O ESD MOS device gate to form second device HV-LDD implants and HV-I/O ESD MOS device HV-LDD implants. The HV-LDD mask is removed. Spacers are formed over the respective exposed side walls of the gate and oxide layers within each respective region to complete fabrication of a first device, a second device and the HV-I/O ESD MOS device. In an alternate embodiment, an I/O LV device may also be simultaneously formed within an I/O LV device region.